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| L6326 2 CHANNEL VOLTAGE SENSE AMR/GMR PREAMPLIFIERS PRODUCT PREVIEW s s s s s s s s s s s s s s s s s s s s s s s s s s s Power Supplies +5Vdc, +8Vdc Current bias or voltage bias (selectable) / Voltage sense architecture Single ended read input 24 pin TSSOP package, two channels External Resistor for read and write currents or trimmed internal resistor available (serial port selectable) Read channel -3dB bandwidth > 300MHz (Rmr=60 ohms, no interconnect) Input equivalent preamplifier voltage noise 0.5nV/rtHz typ Input equivalent MR bias current noise 10pA/rtHz typ MR bias current programmable (5 bit DAC) 1.88mA (GMR range), 3.8-10mA (AMR range) MR bias voltage programmable (5 bit DAC) 100460mV (GMR range), 220-580mV (AMR range) Programmable gain (100V and 150V) Write frequency up to 250MHz (Lh=90nH,R=15 ohms, Ch=2pF, VDD=8V) Rise/Fall time <0.7ns (Iw =40mA 0-pk, Lh=90nH, Rh=15 ohms, Ch=2pF, VDD=8V) Write current programmable (5 bit DAC) 15-60mA Overshoot control 3 bit resolution (+1 bit for range) Bi-directional 16-bit TTLs Serial interface for head selection, read/write currents selection, chip parameters modification, chip enable, vendor code and fault status read back registers 2-wire mode selection (R/W, MRR) Bank write feature for servo write Digital buffered head voltage DBHV / Analog buffered head voltage ABHV pin (gain 5) Thermal asperity detection with adjustable sensitivity level (6 bit DAC) Thermal asperity correction Read head open/short detection Low supply detect and temperature monitoring (high temperature warning and Analog Temperature Diode Voltage measurement) Low write frequency detection WRITE to READ fast recovery 250ns (same head, including 150ns blanking period) GMR Low-Bias in WRITE mode with fast TSSOP24 ORDERING NUMBER: L6326 s s s s s s recovery to READ mode bias (250ns) Head-to-head switch in READ mode - 10s (typ) Head and MR bias current switching transient current head protection READ-to-WRITE switching 30ns (same head) Programmable read bias during write and bank write operation ESD diodes for GMR protections Differential Write Driver to minimize coupling to GMR element DESCRIPTION The L6326 is a two channel BICMOS monolithic integrated circuit GMR pre-amplifier designed for use with four-terminal magneto-resistive (AMR and GMR heads) read/inductive write heads. The device consists of a voltage sense current bias or voltage bias (selectable), single ended input/ true differential output (RDX, RDY), low-noise high bandwidth read amplifier and includes fast current switching write drivers which support data rates up to 500 Mb/s with 90nH write heads. The GMR pre-amplifier provides programmable read current/voltage bias and write current (5 bit DACs), fault detection circuitry and servo writing features. Read amplifier gain, write current wave shape (overshoot and damping) can be adjusted and a thermal asperity detection and correction circuit can be enabled and programmed with different thresholds (6 bit DAC) through a 16-bit bi-directional serial interface (SDEN, SDATA, SCLK). The device operates from a +5V supply and a +8V supply (typical) for the write drivers. No external components are required if the internal trimmed resistor for reference current setting is selected. 1/4 February 2001 This is preliminary information on a new product now in development. Details are subject to change without notice. L6326 Figure 1. Preamplifier block diagram VCC (+5V) VGND (0V) VDD (+8V) WDX PREDRIVER HW0X HW0Y WRITE DRIVERS WDY 3v FAULT PROCESSO R Low supply detection, Open/short heads, TA detection, low write frequency, high temperature FLT HW1X HW1Y 3v SCLK SDEN 3v SERIAL INTERFACE CONTROL Imr, Iwr WRITE DAC R/W HEAD SELECTION & MODE CONTROL ABHV, MR meas READ DAC MRR ABHV/ ADTV RDX RDY Gain boost current/voltage low bias RW e nable hea select d Rdamp Overshoot SDATA HR0 Temperature monitoring TA detection, TA correction MR READ INPUT STAGES HR 1 VREF L 6326 RREF/NC HGND 2/4 L6326 mm DIM. MIN. A A1 A2 b c D E E1 e L L1 k 0.45 4.30 0.05 0.80 0.19 0.09 7.70 7.80 6.40 4.40 0.65 0.60 1.00 0 min., 8 max. 0.75 0.018 4.50 0.170 1.00 TYP. MAX. 1.20 0.15 1.05 0.30 0.20 7.90 0.002 0.031 0.007 0.003 0.303 MIN. inch TYP. MAX. 0.047 0.006 0.039 0.041 0.012 0.008 0.307 0.252 0.173 0.025 0.024 0.039 0.030 0.177 0.311 OUTLINE AND MECHANICAL DATA TSSOP24 Thin Shrink Small Outline Package 7100777 (JEDEC MO-153-AD) 3/4 L6326 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 4/4 |
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